1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device with a repair scheme.
2. Description of the Related Art
Generally, semiconductor memory devices such as a double data rate synchronous dynamic random access memory (DDR SDRAM), have a plurality of memory cells. The number of the memory cells is increasing as the process technology for fabricating the semiconductor memory devices is developing. Thus, the integration degree of the semiconductor devices is increasing. When one of the memory cells fails, the semiconductor memory device may not perform the intended operation and should be discarded. However, it is not cost efficient, in view of the product yield of the semiconductor memory devices, to discard a semiconductor memory device having a small amount of the failed memory cells. To prevent such inefficiency, redundancy memory cells, as well as normal memory cells are additionally disposed in a semiconductor memory device.
When a normal memory cell fails, a redundancy memory cell may replace the failed normal memory cell, which is referred to as a repair-target memory cell. For example, when the repair-target memory cell is accessed during write and read operations, the redundancy memory cell is accessed instead of the repair-target memory cell. Therefore, when an address corresponding to the repair-target memory cell is received, the semiconductor memory device accesses not the repair-target memory cell but the redundancy memory cell. This is referred to as a repair operation and the semiconductor memory device may continue to stably operate through the repair operation.
For a repair operation, a semiconductor memory device needs a repair fuse circuit as well as redundancy memory cells. The repair fuse circuit stores addresses corresponding to repair-target memory cells, which are referred to as a repair-target addresses. The repair fuse circuit includes a plurality of fuses that may be programmed with the repair-target addresses. The semiconductor memory device performs the repair operation on the failed memory cells using the repair-target addresses programmed in the fuses.
The programming is a series of procedures to store information for example, repair-target addresses, into fuses. A fuse may be a physical type fuse or an electrical type fuse.
When programming the physical type fuse, the fuse may be cut by laser blowing according to information to be programmed. The physical type fuse is also referred to as a laser blowing type fuse since a laser beam is used for cutting. The physical type fuse may be programmed only in a wafer state that is, before being packaged.
When programming the electrical type fuse, the fuse may be ruptured by an overcurrent application according to information to be programmed. Electrical type fuses are classified into an anti-type fuse, which is in a short state when programmed, and a blowing type fuse, which is in an open state when programmed. The electrical type fuse may be programmed even in a package state, and therefore is generally used in the field of the semiconductor memory device design. Currently, a fuse array is frequently used as the repair fuse circuit.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a word line control section 110, a repair fuse section 120, a memory cell array 130, and a data input/output section 140.
The word line control section 110 controls a plurality of word lines NOR_WL<1:#> and RDN_WL<1:@> to be activated in response to an external address ADD_EXT and hitting information INF_HT<1:@>. The word lines NOR_WL<1:#> and RDN_WL<1:@> are divided into a plurality of normal word lines NOR_WL<1:#> corresponding to a normal memory cell array 131, and a plurality of redundancy word lines RDN_WL<1:@> corresponding to a redundancy memory cell array 132.
The repair fuse section 120 generates the hitting information INF_HT<1:@> by comparing the external address ADD_EXT, and repair-target addresses, which are programmed therein. The hitting information INF_HT<1:@> corresponds to the redundancy word lines RDN_WL<1:@>, and have information on an activation of the redundancy word lines RDN_WL<1:@> instead of the normal word lines NOR_WL<1:#>. As described above, the repair fuse section 120 is programmed with the repair-target address.
The memory cell array 130 includes a plurality of memory cells coupled to the normal word lines NOR_WL<1:#> of the normal memory cell array 131 and the redundancy word lines RDN_WL<1:@> of the redundancy memory cell array 132. The normal memory cell array 131 stores normal data, and the redundancy memory cell array 132 replaces the normal memory cell array 131 when the normal memory cell array 131 has one or more failed memory cells.
The data input/output section 140 exchanges data between the memory cell array 130 and an external. The data input/output section 140 transfers data DAT from the memory cell array 130 to the external during an read operation and from the external to the memory cell array 130 during a write operation.
Currently, new concerns in a semiconductor memory device, which were not an issue in the past, are brought up as the process technology and the design technology are developing. The semiconductor memory device takes various tests before being released into the market and the tests should be modified or augmented for the new concerns. A test operation is a major factor for the competiveness of semiconductor memory devices, and it may be important to optimize and effectively control the test.